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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 february 1995 integrated circuits philips semiconductors saa5290 one page economy teletext/tv microcontroller
february 1995 2 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 features general complete one page teletext decoder and tv microcontroller in a single 52-pin package eastern european, western european and turkish language variants covered in one device double size, double width and double height character capability for on-screen display (osd) enhanced display features including meshing and shadowing separate display and acquisition timing for increased flexibility minimum peripheral component count 525 line and 625 line display synchronization standby mode through power-down of teletext and analog hardware. microcontroller 16 kbytes masked rom (16 kbytes eeprom variant for product development) 256 bytes of on-chip ram six 6-bit pulse width modulators (pwm) and one 14-bit precision pwm 4-bit digital-to-analog converter (dac) and comparator with a 3-input multiplexer allowing implementation of 3 analog-to-digital converters (adc) in software 2 high current (10 ma) open-drain outputs interrupt logic 0 triggered on rising and falling edges, providing pulse-width measurement for remote control decoding master and slave bit-level i 2 c-bus hardware. description the saa5290 is a single-chip one page teletext decoder and television control microcontroller. the device will decode 625-line based world system teletext transmissions and provides television control functions and on-screen display (osd) functions. the teletext decoder hardware is a derivative of the saa5254 (ivt1.1x), and the tv control functionality provided by an on-chip industrial standard 80c51 microcontroller. a single-page static ram is included on-board providing a complete one page teletext decoder and osd memory. the saa5290 is available as a mask-programmed rom version. an eeprom version is also available for product development. both versions are available in an sdip52 package. ordering information notes 1. nnn is a three-digit number referencing the microcontroller program rom mask. 2. i is a digit number referring to the language variant of the saa5290zp/nv. type number memory package name description version saa5290zp/nnn (1) rom sdip52 plastic shrink dual in-line package; 52 leads (600 mil) sot247-1 saa5290zp/nvi (2) eeprom sdip52 plastic shrink dual in-line package; 52 leads (600 mil) sot247-1
february 1995 3 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 quick reference data block diagram symbol parameter min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v i ddm microcontroller supply current - 25 40 ma i dda analog supply current - 35 50 ma i ddt teletext supply current - 20 30 ma f xtal crystal frequency - 12 - mhz t amb operating ambient temperature - 20 - +70 c fig.1 block diagram. handbook, full pagewidth mlc102 data slicer acquisition timing teletext acquisition display timing display page ram oscillator 80c51 micro- controller analog-to- digital converter pulse width modulator timer/ ctrs/ i c 2 data address 16k x 8 rom port 3 9 to 12, 30 5 256 x 8 ram port 2 1 to 8 8 text interface port 1 45 to 52 8 port 0 14 to 21 8 p3.0 to p3.4/ adc0 to adc2 p2.0 to p2.7 pwm p1.0 to p1.7 / int0, int1, t0, t1, sda, scl p0.0 to p0.7 v ssa 22 v ssd2 v ssd1 28 13 43 reset 40 oscgnd 42 oscout 41 oscin saa5290 37 vsync 36 hsync 27 frame rgbref 34, 33, 32 r, g, b 35 31 vds 29 cor 25 26 black iref cvbs0 cvbs1 23, 24 2 38 39 44 v ddm v ddt v dda 3
february 1995 4 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 pinning symbol pin description p2.0/tpwm 1 port 2 : 8-bit open-drain bidirectional port with alternative functions. p2.0/tpwm is the output for the 14-bit high precision pwm. p2.1/pwm0 to p2.6/pwm5 are the outputs for the 6-bit pwms 0 to 5. p2.1/pwm0 2 p2.2/pwm1 3 p2.3/pwm2 4 p2.4/pwm3 5 p2.5/pwm4 6 p2.6/pwm5 7 p2.7 8 p3.0/adc0 9 port 3 : 5-bit open-drain bidirectional port with alternative functions. p3.0/adc0 to p3.2/adc2 are the inputs for the software adc facility. p3.1/adc1 10 p3.2/adc2 11 p3.3 12 p3.4 30 v ssd1 13 digital ground 1 for teletext and microcontroller circuits. p0.0 14 port 0 : 8-bit open-drain bidirectional port. p0.5 and p0.6 have 10 ma current sinking capability at 0.5 v for direct drive of leds. p0.1 15 p0.2 16 p0.3 17 p0.4 18 p0.5 19 p0.6 20 p0.7 21 v ssa 22 analog ground. cvbs0 23 composite video input. a positive-going 1 v (peak-to-peak) input is required, connected via a 100 nf capacitor. cvbs1 24 black 25 video black level storage input. this pin should be connected to v ssa via a 100 nf capacitor. iref 26 reference current input for analog circuits, connected to v ssa via a 27 k w resistor. frame 27 de-interlace output synchronized with the vsync pulse to produce a non-interlaced display by adjustment of the vertical de?ection currents. v ssd2 28 digital ground 2. cor 29 open-drain, active low output which allows selective contrast reduction of the tv picture to enhance a mixed mode display. rgbref 31 dc input voltage to de?ne the output high level on the rgb pins. b 32 dot rate character output of the blue colour information. g 33 dot rate character output of the green colour information. r 34 dot rate character output of the red colour information. vds 35 video/data switch push-pull output for dot rate fast blanking. hsync 36 horizontal sync dedicated input for a ttl-level version of the horizontal sync pulse. the polarity of this pulse is programmable by register bit txt1.h polarity.
february 1995 5 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 vsync 37 vertical sync dedicated input for a ttl-level version of the vertical sync pulse. the polarity of this pulse is programmable by register bit txt1.v polarity. v dda 38 +5 v analog power supply. v ddt 39 +5 v teletext power supply. oscgnd 40 crystal oscillator ground. oscin 41 12 mhz crystal oscillator input. oscout 42 12 mhz crystal oscillator output. reset 43 if the reset input is high for 2 machine cycles (24 oscillator periods) while the oscillator is running, the saa5290 is reset. this pin should be connected to v ddm via a 2.2 m f capacitor. v ddm 44 +5 v microcontroller power supply. p1.0/int1 45 port 1 : 8-bit open-drain bidirectional port with alternative functions. p1.0/int1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse. p1.1/t0 is the counter/timer 0. p1.2/int0 is external interrupt 0. p1.3/t1 is the counter/timer 1. p1.6/scl is the serial clock input for i 2 c-bus. p1.7/sda is the serial data port for the i 2 c-bus. p1.1/t0 46 p1.2/int0 47 p1.3/t1 48 p1.6/scl 49 p1.7/sda 50 p1.4 51 p1.5 52 symbol pin description
february 1995 6 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 fig.2 pin configuration. handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 22 23 24 25 26 21 42 41 43 44 45 46 47 48 49 50 51 52 mlc103 saa5290 p2.0/tpwm p2.1/pwm0 p2.2/pwm1 p2.3/pwm2 p2.4/pwm3 p2.5/pwm4 p2.6/pwm5 p2.7 p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 cvbs0 cvbs1 black iref ssd1 v ddm v ddt v dda v ssd2 v ssa v p1.5 p1.4 p1.7/sda p1.6/scl p1.3/t1 p1.2/int0 p1.1/t0 p1.0/int1 reset oscout oscin oscgnd vsync hsync vds r g b rgbref p3.4 cor frame
february 1995 7 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 quality and reliability this device will meet philips semiconductors general quality specification for business group consumer integrated circuits snw-fq-611-part e (see quality reference handbook , order number 9398 510 63011). the principal requirements are shown in tables 1 to 4. group a table 1 acceptance tests per lot group b table 2 processability tests (by package family) group c table 3 reliability tests (by process family) table 4 reliability tests (by device type) notes to tables 1 to 4 1. ppm = fraction of defective devices, in parts per million. ltpd = lot tolerance percent defective. fpm = fraction of devices failing at test condition, in failures per million. fits = failures in time standard. test requirements (1) mechanical cumulative target: < 80 ppm electrical cumulative target: < 80 ppm test requirements (1) solderability < 7% ltpd mechanical < 15% ltpd solder heat resistance < 15% ltpd test conditions requirements (1) operational life 168 hours at t j = 150 c < 1500 fpm; equivalent to < 100 fits at t j =70 c humidity life temperature, humidity, bias 1000 hours, 85 c, 85% rh (or equivalent test) < 2000 fpm temperature cycling performance t stg(min) to t stg(max) < 2000 fpm test conditions requirements (1) esd and latch-up esd human body model 2000 v, 100 pf, 1.5 k w < 15% ltpd esd machine model 200 v, 200 pf, 0 w < 15% ltpd latch-up 100 ma, 1.5 v dd (absolute maximum) < 15% ltpd
february 1995 8 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 limiting values in accordance with absolute maximum rating system (iec 134). notes 1. this maximum value has an absolute maximum of 6.5 v independent of v dd . 2. except in standby mode. characteristics v dd =5v 10%; v ss =0v; t amb = - 20 to +70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage (all supplies) - 0.3 +6.5 v v i input voltage (any input) note 1 - 0.3 v dd + 0.5 v v o output voltage (any output) note 1 - 0.3 v dd + 0.5 v i o output current (each output) - 10 ma i iok dc input or output diode current - 20 ma d v ss difference between v ssd , v ssa and oscgnd - 0.1 v d v dd difference between v ddm , v ddt and v dda note 2 - 0.1 v t amb operating ambient temperature - 20 +70 c t stg storage temperature - 55 +125 c symbol parameter conditions min. typ. max. unit supplies v dd supply voltage (v dd to v ss ) 4.5 5.0 5.5 v i ddm microcontroller supply current - 25 40 ma i dda analog supply current - 35 50 ma i ddt teletext supply current - 20 30 ma digital inputs reset v il low level input voltage - 0.3 - 0.2v dd - 0.1 v v ih high level input voltage 0.7v dd - v dd + 0.3 v i li input leakage current v i = 0 to v dd - 10 - +10 m a c i input capacitance -- 4pf hsync and vsync v thf switching threshold falling 0.2v dd -- v v thr switching threshold rising -- 0.8v dd v v hys hysteresis voltage - 0.33v dd - v c i input capacitance -- 4pf
february 1995 9 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 digital outputs r, g and b (note 1) v ol low level output voltage i ol = 2 ma 0 - 0.2 v v oh high level output voltage i oh = - 2ma v rgbref - 0.3 v rgbref v rgbref + 0.4 v | z o | output impedance -- 150 w c l load capacitance -- 50 pf i o dc output current --- 4ma t r output rise time between 10% and 90%; c l =50pf -- 20 ns t f output fall time between 90% and 10%; c l =50pf -- 20 ns cor ( open - drain output ) v oh high level pull-up output voltage -- v dd v v ol low level output voltage i ol = 2 ma 0 - 0.5 v i ol low level output current -- 2ma c l load capacitance -- 25 pf vds v ol low level output voltage i ol = 1.6 ma 0 - 0.2 v v oh high level output voltage i oh = - 1.6 ma v dd - 0.3 - v dd + 0.4 v c l load capacitance -- 50 pf t r output rise time between 10% and 90%; c l =50pf -- 20 ns t f output fall time between 90% and 10%; c l =50pf -- 20 ns r, g, b and vds t skew skew delay between any two pins -- 20 ns frame v oh high level output voltage i ol = 8 ma 0 - 0.5 v v ol low level output voltage i ol = - 8ma v dd - 0.5 - v dd v i ol low level output current - 8 - +8 ma c l load capacitance -- 100 pf symbol parameter conditions min. typ. max. unit
february 1995 10 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 digital input/outputs p0.0 to p0.4, p0.7, p1.0 to p1.5, p2.0 to p2.7 and p3.0 to p3.5 v il low level input voltage - 0.3 - 0.2v dd - 0.1 v v ih high level input voltage 0.2v dd + 0.9 - v dd + 0.3 v c i input capacitance -- 4pf v ol low level output voltage i ol = 3.2 ma 0 - 0.45 v c l load capacitance -- 50 pf p0.5 and p0.6 v il low level input voltage - 0.3 - 0.2v dd - 0.1 v v ih high level input voltage 0.2v dd + 0.9 - v dd + 0.3 v c i input capacitance -- 4pf v ol low level output voltage i ol =10ma 0 - 0.45 v c l load capacitance -- 50 pf p1.6 and p1.7 v il low level input voltage - 0.3 - +1.5 v v ih high level input voltage 3.0 - v dd + 0.3 v c i input capacitance -- 5pf v ol low level output voltage i ol = 3 ma 0 - 0.5 v c l load capacitance -- 400 pf t f output fall time between 3 and 1 v -- 200 ns analog inputs cvbs0 and cvbs1 v sync sync voltage amplitude 0.1 0.3 0.6 v v vid(p-p) video input voltage amplitude (peak-to-peak value) 0.7 1.0 1.4 v z source source impedance -- 250 w v ih high level input voltage 3.0 - v dd + 0.3 v | z i | input impedance 2.5 5.0 - k w c i input capacitance -- 10 pf iref r gnd resistor to ground - 27 - k w rgbref (note 1) v i input voltage - 0.3 - v dd v i i dc input current -- 12 ma symbol parameter conditions min. typ. max. unit
february 1995 11 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 notes 1. all rgb current is sourced from the rgbref pin. the maximum effective series resistance between rgbref and the r, g and b pins is 150 w . 2. crystal order number 4322 143 05561. adc0, adc1 and adc2 v il low level input voltage - 0.3 - v dd v analog input/output black c black storage capacitor to ground - 100 - nf v black black level voltage for nominal sync amplitude 1.8 2.15 2.5 v i li input leakage current - 10 - +10 m a crystal oscillator oscin v il low level input voltage - 0.3 - 0.2v dd - 0.1 v v ih high level input voltage 0.7v dd - v dd + 0.3 v c i input capacitance -- 10 pf oscout f osc crystal oscillator frequency - 12 - mhz c o output capacitance -- 10 pf c rystal specification (note 2) f xtal nominal frequency - 12 - mhz c l load capacitance - 32 - pf c1 series capacitance t amb =25 c - 18.5 - ff c0 parallel capacitance t amb =25 c - 4.9 - pf r r resonance resistance t amb =25 c - 35 -w t xtal temperature range - 20 +25 +70 c x j adjustment tolerance t amb =25 c -- 50 10 - 6 x d drift -- 30 10 - 6 symbol parameter conditions min. typ. max. unit
february 1995 12 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 table 5 characteristics for the i 2 c-bus interface notes 1. this parameter is determined by the user software. it must comply with the i 2 c-bus specification. 2. this value gives the auto-clock pulse length which meets the i 2 c-bus specification for the special crystal frequency. alternatively, the scl pulse must be timed by software. 3. the rise time is determined by the external bus line capacitance and pull-up resistor. it must be less than 1 m s. 4. the maximum capacitance on bus lines sda and scl is 400 pf. symbol parameter input output i 2 c-bus specification scl timing t hd;sta start condition hold time 3 4.0 m s note 1 3 4.0 m s t low scl low time 3 4.7 m s note 1 3 4.7 m s t high scl high time 3 4.0 m s 3 4.0 m s; note 2 3 4.0 m s t rc scl rise time 1.0 m s note 3 1.0 m s t fc scl fall time 0.3 m s 0.3 m s; note 4 0.3 m s sda timing t su;dat1 data set-up time 3 250 ns note 1 3 250 ns t hd;dat data hold time 3 0 ns note 1 3 0ns t su;sta repeated start set-up time 3 4.7 m s note 1 3 4.7 m s t su;sto stop condition set-up time 3 4.0 m s note 1 3 4.0 m s t buf bus free time 3 4.7 m s note 1 3 4.7 m s t rd sda rise time 1.0 m s note 3 1.0 m s t fd sda fall time 0.3 m s 0.3 m s; note 4 0.3 m s d th t rd t fd t rc t fc t hd;sta t low t high t su;dat1 t hd;dat t su;dat2 t su;dat3 0.7v dd 0.3v dd t su;sto t buf t su;sta sda (input / output) scl (input / output) start condition repeated start condition stop condition start or repeated start condition 0.7v dd 0.3v dd mlc104 fig.3 i 2 c-bus interface timing.
february 1995 13 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 functional description introduction the saa5290 is an integrated teletext decoder and microcontroller. the teletext decoder is derived from the saa5254 single page teletext decoder ic, with a number of enhancements to increase its suitability for on-screen display applications. the microcontroller is a derivative of the industry standard 80c51 microcontroller. a block diagram of the saa5290 is given in fig.1. microcontroller the functionality of the microcontroller used on the saa5290 is described here with reference to the industry standard 80c51 microcontroller. a full description of its functionality can be found in the handbook 80c51-based 8-bit microcontrollers ic20 . using the 80c51 as a reference, the changes made for the saa5290 fall into two categories, features not supported by the saa5290 and features found on the saa5290 but not supported by the 80c51. 80c51 features not supported by the saa5290 i nterrupt priority the ip sfr is not implemented and all interrupts are treated with the same priority level. the saa5290 retains the normal prioritization of interrupts within a level. table 6 interrupts and their vector addresses event program memory address reset 000h external int0 003h timer 0 00bh external int1 013h timer 1 01bh i 2 c-bus 053h o ff - chip memory the saa5290 does not support the use of off-chip program memory or off-chip data memory. this means that the saa5290 does not have any of ea, rd, wr, ale or psen pins. the 4 movx instructions which move data to and from external ram should not be used. i dle and power - down modes idle and power-down modes are not supported by the saa5290. as a consequence, the respective bits in pcon are not available. uart function the 80c51 uart is not available in the saa5290. as a consequence the scon and sbuf sfrs are removed and the es bit in the ie sfr is unavailable. additional features for the saa5290 the following features are provided by the saa5290 in addition to the standard 80c51 features. i nterrupts the external int1 interrupt is modified to generate an interrupt on both the rising and falling edges of the int1 pin, when ex1 bit is set. this facility allows for software pulse width measurement for handling of a remote control. b it level i 2 c- bus interface the bit-level serial i/o supports the i 2 c-bus. p1.6/scl and p1.7/sda are the serial i/o pins. these two pins meet the i 2 c-bus specification concerning the input levels and output drive capability. consequently, these pins have an open-drain output configuration. all the four following modes of the i 2 c-bus are supported. master transmitter master receiver slave transmitter
february 1995 14 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 slave receiver. the advantages of the bit-level i 2 c-bus hardware, compared with a full software i 2 c-bus implementation are: the hardware can generate the scl pulse testing a single bit (rbf or wbf respectively) is sufficient as a check for error-free transmission. the bit-level i 2 c-bus hardware operates on serial bit level and performs the following functions: filtering the incoming serial data and clock signals recognizing the start condition generating a serial interrupt request si after reception of a start condition and the first falling edge of the serial clock recognizing the stop condition recognizing a serial clock pulse on the scl line latching a serial bit on the sda line (sdi) stretching the scl low period of the serial clock to suspend the transfer of the next serial data bit setting read bit finished (rbf) when the scl clock pulse has finished and write bit finished (wbf) if there is no arbitration loss detected (i.e. sda = logic 0 while sdo = logic 1) setting a serial clock low-to-high detected (clh) flag setting a bus busy (bb) flag on a start condition and clearing this flag on a stop condition releasing the scl line and clearing the clh, rbf and wbf flags to resume transfer to the next serial data bit generating an automatic clock if the single bit data register s1bit is used in master mode. the following functions must be done in software: handling the i 2 c-bus start interrupts converting serial data to parallel data when receiving converting parallel data to serial data when transmitting comparing the received slave address with its own address interpreting the acknowledge information guarding the i 2 c-bus status if rbf or wbf = logic 0. additionally, if acting as master: generating start and stop conditions handling bus arbitration generating serial clock pulses if s1bit is not used. three sfrs support the function of the bit-level i 2 c-bus hardware, they are s1int, s1bit and s1scs. led support port pins p0.5 and p0.6 have a 10 ma current sinking capability to enable leds to be driven directly. pwm dac s the saa5290 has six 6-bit pwm dacs and one14-bit pwm dac. these allow direct control of other parts of the television. the low resolution 6 bit dacs are controlled by their corresponding sfr (pwm0 to pwm5) and are connected as alternative outputs of port p2. the port bit corresponding to the pwm should be set to logic 1 for correct operation of the pwm. table 7 special function registers pwm0 to pwm5 if the pwe bit for a particular port is set to logic 1, the pwm is active and controls its assigned port pin. if the pwe bit is set to logic 0 the corresponding port pin is controlled by the bit in the corresponding port register for that port. the output of the pwm is a pulse of period 21.33 m s with a duty cycle determined by the binary value, pv5 to pv0, multiplied by 0.33 m s. the 14 bit pwm is controlled with sfr registers tdacl and tdach. table 8 special function register tdacl table 9 special function register tdach if the pwe bit is set to logic 1, the tpwm is active and controls port p2.0. if the pwe bit is set to logic 0 the port pin is controlled by the bit in the corresponding port register for p2.0. the output of the tpwm is a pulse of period 42.66 m s with a duty cycle determined by the binary value, td13 to td7, multiplied by 0.33 m s. d7 d6 d5 d4 d3 d2 d1 d0 pwe - pv5 pv4 pv3 pv2 pv1 pv0 d7 d6 d5 d4 d3 d2 d1 d0 td7 td6 td5 td4 td3 td2 td1 td0 d7 d6 d5 d4 d3 d2 d1 d0 pwe - td13 td12 td11 td10 td9 td8
february 1995 15 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 the 7 least significant bits, td6 to td0, extend the high time of a proportion of the pulses by 0.33 m s. if the lsb is set then 1 in 128 cycles is extended, if bit 1 is set then 1 in 64 cycles is extended, and so on. s oftware adc up to 3 successive approximation adcs can be implemented in software by making use of the on-board 4-bit dac and multiplexed voltage comparator. the software adc uses 3 analog inputs which are multiplexed with p3.0 to p3.2. the control of the adc is achieved using the sad sfr. sad.5 and sad.6 select one of the three inputs to pass to the comparator. the other input comes from the dac whose input is set by sad bits 0 to 3. the output of the comparator is sad bit 7 and is valid by the next instruction after starting the comparison by setting sad.st to logic 1. microcontroller interfacing the 80c51 cpu communicates with the peripheral functions using special function registers (sfrs) which are addressed as ram locations. the registers in the teletext decoder appear as normal sfrs in the microcontroller memory map, but are written to using a serial bus. this bus is controlled by dedicated hardware which uses a simple handshake system for software synchronization. the sfr memory map is given in table 10.
february 1995 16 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 table 10 saa5290 special function register map (note 1) symbol descr. direct addr. (hex) bit address, symbol or alternative port function reset value (hex) msb lsb acc (2) accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h b (2) b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dptr: data pointer (2 bytes): dph high byte 83h -------- 00h dpl low byte 82h -------- 00h ie (2)(3) interrupt enable a8h af ae ad ac ab aa a9 a8 x 0h ea es1 ** et1 ex1 et0 ex0 p0 (2) port 0 80h 87 86 85 84 83 82 81 80 ffh p1 (2) port 1 90h 97 96 95 94 93 92 91 90 ffh p2 (2) port 2 a0h a7 a6 a5 a4 a3 a2 a1 a0 ffh p3 (2)(3) port 3 b0h -- - b4 b3 b2 b1 b0 xxx 11111b pcon (3) power control 87h ** * * gf1 gf0 ** xxxx 00 xx b psw (2) program status word d0h d7 d6 d5 d4 d3 d2 d1 d0 000000 x 0b cy ac f0 rs1 rs0 0v * p pwm0 (3) pulse width modulator 0 d5h pwe * pv5 pv4 pv3 pv2 pv1 pv0 - pwm1 (3) pulse width modulator 1 d6h pwe * pv5 pv4 pv3 pv2 pv1 pv0 - pwm2 (3) pulse width modulator 2 d7h pwe * pv5 pv4 pv3 pv2 pv1 pv0 - pwm3 (3) pulse width modulator 3 dch pwe * pv5 pv4 pv3 pv2 pv1 pv0 - pwm4 (3) pulse width modulator 4 ddh pwe * pv5 pv4 pv3 pv2 pv1 pv0 - pwm5 (3) pulse width modulator 5 deh pwe * pv5 pv4 pv3 pv2 pv1 pv0 - s1bit (3) serial i 2 c data d9h sdi/ sdo ******* 00h
february 1995 17 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 s1int (3) serial i 2 c interrupt dah si *******- s1scs (2)(3) serial i 2 c control d8h df de dd dc db da d9 d8 - sdi/ sdo sci/ sdo clh bb rbf wbf str ens sad (2) (3) software atod e8h ef ee ed ec eb ea e9 e8 00h vhi ch1 ch0 st sad3 sad2 sad1 sad0 sp stack pointer 81h 8f 8e 8d 8c 8b 8a 89 88 07h tcon (2) timer/counter control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h tdach tpwm high byte d3h pwe * td13 td12 td11 td10 td9 td8 00h tdacl tpwm low byte d2h td7 td6 td5 td4 td3 td2 td1 td0 00h th0 timer 0 high byte 8ch -------- 00h th1 timer 1 high byte 8dh -------- 00h tl0 timer 0 low byte 8ah -------- 00h tl1 timer 1 low byte 8bh -------- 00h tmod timer/counter mode 89h gate c/ tm1 m0gatec/ t m1 m0 00h txt0 (3) teletext register 0 c0h x24 pos * auto frame disable hdr roll display status row only disable frame ** 00h txt1 (3) teletext register 1 c1h * 8-bit acq off x26 full field field polarity h polarity v polarity 00h txt2 (3) teletext register 2 c2h ** * * * sc2 sc1 sc0 00h txt3 (3) teletext register 3 c3h ** * prd4 prd3 prd2 prd1 prd0 00h symbol descr. direct addr. (hex) bit address, symbol or alternative port function reset value (hex) msb lsb
february 1995 18 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 notes 1. the star ( * ) indicates these bits are inactive and must be written to logic 0 for future compatibility. 2. sfrs are bit addressable. 3. sfrs are modified or added to the 80c51 sfrs. txt4 (3) teletext register 4 c4h ** east/ west * b mesh enable c mesh enable trans enable shadow enable 00h txt5 (3) teletext register 5 c5h bkgnd out bkgnd in cor out cor in text out text in picture on out picture on in 00000011b txt6 (3) teletext register 6 c6h bkgnd out bkgnd in cor out cor in text out text in picture on out picture on in 00000011b txt7 (3) teletext register 7 c7h status row top cursor on conceal /reveal t op/ btm sng/dbl height box on 24 box on 1-23 box on 0 00h txt8 (3) teletext register 8 c8h ** * * * * * cvbs0/ cvbs1 00h txt9 (3) teletext register 9 c9h * clear mem. a0 r4 r3 r2 r1 r0 00h txt10 (3) teletext register 10 cah ** c5 c4 c3 c2 c1 c0 00h txt11 (3) teletext register 11 cbh d7 d6 d5 d4 d3 d2 d1 d0 00h txt12 (3) teletext register 12 cch 625/525 sync rom ver r4 rom ver r3 rom ver r2 rom ver r1 rom ver r0 txt on video quality txt13 (2)(3) teletext register 13 b8h bf be bd bc bb ba b9 b8 00h ** * * * * * txt i/face busy symbol descr. direct addr. (hex) bit address, symbol or alternative port function reset value (hex) msb lsb
february 1995 19 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 table 11 sfr description register function ie - interrupt enable ea disable all interrupts (logic 0) or use individual enable bits (logic 1). es1 i 2 c-bus interrupt enable (logic 1). et1 enable timer 1 over?ow interrupt (logic 1). ex1 enable external interrupt 1 (logic 1). et0 enable timer 0 over?ow interrupt (logic 1). ex0 enable external interrupt 0 (logic 1). pcon - power control gf0 general purpose ?ag bit 0. gf1 general purpose ?ag bit 1. pwm0 to pwm5 - 6-bit pulse width modulator control registers pwe activate this 6-bit pwm and take over port pin (logic 1). pv0 to pv5 value to output by this 6-bit pwm. sad - software adc control vhi analog input voltage greater than dac output voltage (logic 1). ch0 and ch1 see table 12. st initiate voltage comparison (logic 1). this is automatically reset. sad0 to sad3 4-bit dac input value. the dac output of this value is compared with analog input voltage. s1bit - serial i 2 c-bus data (read) sdi i 2 c-bus data bit latched-in from sda on the last rising edge of scl. s1bit - serial i 2 c-bus data (write) sdo i 2 c-bus data bit output. s1int - serial i 2 c-bus interrupt si i 2 c-bus interrupt ?ag. s1scs - serial i 2 c-bus control (read) sdi serial data input at sda. sci serial clock input at scl. clh clock low-to-high transition ?ag. bb bus busy ?ag. rbf read bit ?nished ?ag. wbf write bit ?nished ?ag. str clock stretching enable (logic 1). ens enable serial i/o (logic 1).
february 1995 20 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 s1scs - serial i 2 c-bus control (write) sdo serial data output at sda. sco serial clock output at scl. clh clock low-to-high transition. str clock stretching enable (logic 1). ens enable serial i/o (logic 1). tdach - 14-bit pwm msb register pwe activate this 14-bit pwm and take over port pin (logic 1). td8 to td13 6 lsbs of this value to be output by the 14-bit pwm. tdacl - 14-bit pwm lsb register td0 to td7 8 lsbs of this value to be output by the 14-bit pwm. txt0 - teletext register 0 (write only) x24 position store packet 24 in extension packet memory (logic 0) or page memory (logic 1). auto frame frame output switched off automatically if any video displayed (logic 1). disable hdr roll do not write rolling headers and time into memory (logic 1). status row only display only memory row (logic 1). disable frame frame output always low (logic 1). txt1 - teletext register 1 (write only) 8-bit data in packets 0 to 24 written into memory without error checking (logic 1). acq off prevent teletext acquisition section writing to memory (logic 1). x26 disable automatic processing of packet 26 data (logic 1). full field accept teletext on tv lines 2 to 22 only (logic 0) or on any line (logic 1). field polarity vsync in ?rst half of the line (logic 0) or second half of the line (logic 1) at start of even ?eld. h polarity hsync input positive-going (logic 0) or negative-going (logic 1). v polarity vsync input positive-going (logic 0) or negative-going (logic 1). txt2 - teletext register 2 (write only) sc0 to sc2 start column at which page request data written into txt3 sfr is placed. txt3 - teletext register 3 (write only) prd0 to prd4 page request data. txt4 - teletext register 4 (write only) b mesh enable enable meshing of area with black background (logic 1). c mesh enable enable meshing of area with other background colours (logic 1). trans enable black background colour is transparent i.e. video is displayed (logic 1). shadow enable enable south-east shadowing (logic 1). east/ west western european languages displayed (logic 0) or eastern european languages displayed (logic 1). register function
february 1995 21 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 txt5 - teletext register 5 (write only) bkgnd out background colour displayed outside teletext boxes (logic 1). bkgnd in background colour displayed inside teletext boxes (logic 1). cor out cor output active outside teletext boxes (logic 1). cor in cor output active inside teletext boxes (logic 1). text out text displayed outside teletext boxes (logic 1). text in text displayed inside teletext boxes (logic 1). picture on out video picture displayed outside teletext boxes (logic 1). picture on in video picture displayed inside teletext boxes (logic 1). txt6 - teletext register 6 (write only) - this register has the same meaning as txt5 but is only invoked if either newsflash (c5) or the subtitle (c6) bit in row 25 of the basic page memory is set. txt7 - teletext register 7 (write only) status row top display row 24 below (logic 0) or above (logic 1) teletext page. cursor on display cursor at location pointed to by txt9 and txt10 (logic 1). conceal/reveal display characters in areas with the conceal attribute set (logic 1). t op/bottom display rows 0 to 11 (logic 0) or 12 to 23 (logic 1) when the double height bit is set. sng/dbl height display each character at twice normal height (logic 1). box on 24 enable teletext boxes in memory row 24 (logic 1). box on 1-23 enable teletext boxes in memory rows 1 to 23 (logic 1). box on 0 enable teletext boxes in memory row 0 (logic 1). txt8 - teletext register 8 (write only) cvbs0/cvbs1 cvbs0 input (logic 0) or cvbs1 (logic 1) inputs used for teletext. txt9 - teletext register 9 (write only) clear memory write 20h into every location in teletext memory (logic 1). a0 access basic page memory (logic 0) or extension packet memory (logic 1) with txt11 sfr. r0 to r4 memory row to be accessed with txt11 sfr. txt10 - teletext register 10 (write only) c0 to c5 memory column to be accessed with txt11 sfr. txt11 - teletext register 11 d0 to d7 data byte written to, or read from, teletext memory. register function
february 1995 22 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 table 12 ch1 and ch0 selection txt12 - teletext register 12 (read only) 625/525 sync a 625 line cvbs signal (logic 0), or a 525 line cvbs signal (logic 1) is being input. rom ver r0 to r4 mask programmable to identify character set version. txt on teletext power has been applied to the device (logic 1). video quality cvbs input can be locked on by the teletext decoder (logic 1). txt13 - teletext register 13 (read only) txt i/face busy text interface busy and no access for either read or write is allowed to sfrs txt0 to txt11 (logic 1). this register bit performs the software handshake to the teletext control registers. ch1 ch0 input pin 0 0 none 0 1 adc0 1 0 adc1 1 1 adc2 register function
february 1995 23 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 teletext decoder functional description data slicer the data slicer extracts the digital teletext data from the incoming analog waveform. this is performed by sampling the cvbs waveform and processing the samples to extract the teletext data and clock. acquisition timing the acquisition timing is generated from a logic level positive-going composite sync signal vcs. this signal is generated by the sync separator circuit which adaptively slices the sync pulses at 50% of their height. it is able to do this over a wide range of sync amplitudes by using the same basic principle used on vip1 (saa5230) and vip2 (saa5231). figure 4 is a block diagram showing the principles of operation. it relies upon the fact that the ratio of the sync width to the line time is approximately 13 : 1. in order to slice the sync pulse at the correct 50% level two currents are generated. one is constant and is proportional to the difference between the black level of the video and the slicing level. the other is produced only when the video is below the slicing level, and is also proportional to the difference between the slicing level and the input, but has a magnitude13 times greater. the black level is determined by a sync-gated peak detector. the video is negatively peak detected into an external capacitor (black, pin 25), but not during the sync pulse vcs. the two currents are integrated on the cvbs input coupling capacitor and the net effect is to alter the mean input voltage until the (fixed) slicing level is correct. the acquisition clocking and timing are locked to the vcs signal using a digital phased-locked-loop. the phase error in the acquisition phase-locked-loop is detected by a signal quality circuit which disables acquisition if poor signal quality is detected. fig.4 sync separator block diagram. handbook, full pagewidth mlc105 v dd v ref v ref v ref cvbs (= slicing level) filter filter gated negative peak detector black vcs 1/3v (ma) i 1/39v (ma) i
february 1995 24 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 teletext acquisition the saa5290 is able to acquire 625-line world system teletext. teletext is acquired under control of the on-board 80c51 microcontroller. pages are requested by writing a series of bytes into the txt3 sfr which corresponds to the number of the page required. the bytes written into txt3 are put into a small ram with an auto-incrementing address. the start address for the ram is set using the sfr txt2 register. table 13 shows the contents of the page request ram. if the do care bit for part of the page number is set to logic 0 then that part of the page number is ignored when the acquisition section is deciding whether a page being received off air should be stored or not. for example if the do care bits for the 4 subcode digits are all set to logic 0 then every subcode version of the page will be captured. when the hold' bit is set to logic 0 the acquisition section will not recognize any page as having the correct page number and no pages will be captured. table 13 register map for page requests (txt3); note 1 note 1. x = don't care. start column prd4 prd3 prd2 prd1 prd0 0 do care magazine hold mag2 mag1 mag0 1 do care page tens pt3 pt2 pt1 pt0 2 do care page units pu3 pu2 pu1 pu0 3 do care hours tens x x ht1 ht0 4 do care hours units hu3 hu2 hu1 hu0 5 do care minutes tens x mt2 mt1 mt0 6 do care minutes units mu3 mu2 mu1 mu0 page memory organization the acquired teletext packets each contain 40 bytes of data and one packet is stored in each row of the text memory. the page memory organization is given in fig.5. rows 0 to 23 form the teletext page; row 24 is available for status messages and flof/fastext prompt information.
february 1995 25 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 fig.5 basic page memory organization. handbook, full pagewidth mlc106 7 characters for status 8 characters usually rolling (time) fixed character written by hardware, alphanumerics white nor- mally, alphanumerics green when looking for display page 6 178 39 31 32 24 characters from page header rolling when display page looked for 5 to 20 0 1 2 3 4 row 21 22 23 24 25 main page display area packet x / 22 packet x / 23 packet x24 stored here if txt0.7 = 1 10 14 10 bytes for received page information 14 bytes free for use by microcontroller r ow 0 (see fig.5) row 0 is for the page header. the first seven characters (0 to 6) are free for status messages. character 8 is an alphanumeric white or green control character, written automatically by saa5290 to give a green rolling header when a page is being looked for. the last eight characters are for rolling time. r ow 25 (see fig.5) the first 10 bytes of row 25 contain control data relating to the received page as shown in table 14. the remaining 14 bytes are free for use by the microcontroller. extension packet memory organization if txt0.x24 pos bit is set to logic 0, then packet 24 is written into row 0 of the extension memory. packet x27/0 is written to row 1 of the extension memory, with bytes 0 to 37 being hamming checked automatically. packet 8/30 is written to row 2 of the extension memory, with bytes 0 to 6 being 8/4 hamming checked, bytes 7 to 19 unchecked and bytes 20 to 39 odd parity checked. packet 26 processing the saa5290 contains on-board hardware processing of packet 26 data. if a character corresponding to that being transmitted is available in the character set then the correct character code is written into the display memory. fig.6 organization of the extension memory. handbook, halfpage mlc107 packet x24 if txt0.x24 pos = 0 packet x27 / 0 packets 8 / 30 / 0 to 15 1 0 2 row
february 1995 26 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 table 14 row 25 received control data format table 15 page number and sub-code for table 14 row 25 d0 pu0 pt0 mu0 mt0 hu0 ht0 c7 c11 mag0 0 d1 pu1 pt1 mu1 mt1 hu1 ht1 c8 c12 mag1 0 d2 pu2 pt2 mu2 mt2 hu2 c5 c9 c13 mag2 0 d3 pu3 pt3 mu3 c4 hu3 c6 c10 c14 0 0 d4 ham.er ham.er ham.er ham.er ham.er ham.er ham.er ham.er found 0 d5 0 0 0 0 0 0 0 0 0 pblf d60000000000 d70000000000 column 0 1 2 3 4 5 6 7 8 9 bit name description page number mag magazine pu page units pt page tens pblf page being looked for ham.er hamming error in corresponding byte page sub-code mu minutes units mt minutes tens hu hours units ht hours tens c4 to c14 transmitted control bits
february 1995 27 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 display the capabilities of the display are based on the requirements of level 1 teletext, with some enhancements for use with locally generated on-screen displays (osd). the display consists of 25 rows each of 40 characters, with the characters displayed being those from rows 0 to 24 of the basic page memory. the page memory stores 8-bit character codes which correspond to 260 displayable characters and 44 control codes, normally displayed as spaces. each character is defined by a matrix 12 pixels high and 10 pixels deep. when displayed each pixel is 0.5 m s wide and 1 tv line, in each field, high. the saa5290 signals the tv display circuits to display the rgb outputs of the saa5290 rather than video picture by setting vds high. the way in which this signal is switched is controlled by the txt5 and txt6 sfrs. there are three control functions: background on, text on and picture on. there are separate bits for each function for inside and outside teletext boxes and if the newsflash or subtitle bits are set. this allows the software to configure the type of display required. the effect of the combination of these bits is given in table 16. the cor bits in register 5 and register 6 control when the output is pulled low. this output is intended to act on the tv display circuits to reduce the contrast of the video display. the display character set is given in fig.9. the character set provided contains all the characters required to display eastern and western european languages. register bit txt4.east/ west sets whether eastern or western languages are set with the c12 to c14 bits. in order to make on-screen displays easy to use, the saa5290 contains additional display attributes in column 11. control codes are categorized as set at or set after. set at means the code has effect at the current character position and set after means they have effect from the following character. codes 11/0 to 11/7 are always set at. codes 11/11 to 11/15 are set after when defining the start of an osd box and set at when ending an osd box. codes 11/12 to 11/15 force a box condition allowing on-screen display messages to be displayed without having to erase the whole contents of the teletext page. on-screen displays are only available in tv mode and not in text mode. in mixed text and tv mode the displayed screen is not defined if an osd box is encountered in the page memory. table 16 display mode picture on text on background on result 0 0 x text mode, black screen 0 1 0 text mode, background always black 0 1 1 text mode 1 0 x tv mode 1 1 0 mixed mode and tv mode 1 1 1 text mode, tv picture outside text area display timing the display circuitry is driven from the h/vsync inputs, and is independent of the input video signal. consequently hsync and vsync are always required to slave synchronize the display. the frame output of the saa5290 is provided to facilitate de-interlacing the teletext display. the behaviour of frame is controlled via the register bits txt0.disable frame, txt0.auto frame and txt1.field polarity. if the active edge of vsync occurs in the first half of a tv line then the field is even, and if the active edge of vsync is in the second half of a line then the field is odd. the active edge is controlled with txt1.v polarity. with txt0.auto frame low frame is high for an odd field and low for an even field. with txt0.auto frame high frame is only active when text is being displayed, when video is displayed it is forced low. when txt0.disable frame is high frame is always low. if txt1.field polarity is logic 1 then vsync is delayed by 32 m s before being applied to the display timing circuits.
february 1995 28 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 clock generator the oscillator circuit of the saa5290 is a single-stage inverting amplifier in a pierce oscillator configuration. the circuitry between oscin and oscout is basically an inverter biased to the transfer point. a crystal must be used as the feedback element to complete the oscillator circuitry. it is operated in parallel resonance. oscin is the high gain amplifier input and oscout is the output. to drive the saa5290 externally oscin is driven from an external source and oscout is left open-circuit. fig.7 oscillator circuit. (1) the values of c1 and c2 depend on the crystal specification: c1 = c2 = 2c l . handbook, halfpage mlc110 oscout oscin oscgnd c1 (1) c2 (1) fig.8 oscillator circuit driven from external source. handbook, halfpage mlc111 oscout oscin oscgnd not connected external clock not connected
february 1995 29 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 character sets handbook, full pagewidth mlc108 normal height b 3 b 2 b 1 b 0 b 4 b 5 b 6 b 7 0 1 22a3 3a4 5 6 6a 77a 8 9 c column r o w b i t s 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 a 1 0 1 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1 e 1 1 1 0 double width hold graphics f 1 1 1 1 double size release graphics b 1 0 1 1 start box c 1 1 0 0 black back - ground d 1 1 0 1 double height new back - ground a 1 0 1 0 end box separated graphics 9 1 0 0 1 steady contiguous graphics 8 1 0 0 0 flash conceal display 7 0 1 1 1 alpha - numerics white graphics white 6 0 1 1 0 alpha - numerics cyan graphics cyan 5 0 1 0 1 alpha - numerics magenta graphics magenta 4 0 1 0 0 alpha - numerics blue graphics blue 3 0 0 1 1 alpha - numerics yellow graphics yellow 2 0 0 1 0 alpha - numerics green graphics green 0 0 0 0 0 alpha - numerics black graphics black 1 0 0 0 1 alpha - numerics red graphics red b 1 0 1 1 def 1 1 0 1 1 1 1 0 1 1 1 1 def 1 1 0 1 1 1 1 0 1 1 1 1 double width osd double size osd normal size osd double height osd back- ground white back- ground cyan back- ground magenta back- ground blue back- ground yellow back- ground green back- ground black back ground red fig.9 saa5290 european character set.
february 1995 30 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 fig.10 saa5290 european national option characters. handbook, full pagewidth mlc109 language c12 c13 c14 phcb 000 001 010 011 100 french italian swedish german english 2 / 3 2 / 4 4 / 0 5 / b 5 / c 5 / d 5 / e 5 / f 6 / 0 7 / b 7 / c 7 / d 7 / e character position (column / row) spanish 10 e/w 0 111 english 0 0 001 german 1 010 estonian 1 011 german 1 100 german 1 0 0 0 01 11 00 turkish 00 10 101 110 11 1 1 11 rumanian czechoslovakia serbo-croat polish
february 1995 31 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 application information handbook, full pagewidth mlc112 v dd 40 v v tune p2.0/tpwm p2.1/pwm0 p2.2/pwm1 p2.3/pwm2 p2.4/pwm3 p2.5/pwm4 p2.6/pwm5 p2.7 p3.0/adc0 p3.1/adc1 p3.2/adc2 p3.3 v ssd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 v ssa cvbs0 cvbs1 black iref brightness contrast saturation hue volume (l) volume (r) v afc v dd 27 k w 100 nf cvbs (scart) cvbs (if) 100 nf 100 nf v dd v dd p1.5 p1.4 p1.7/sda p1.6/scl p1.3/t1 p1.2/int0 p1.1/t0 p1.0/int1 reset oscout oscin vsync hsync vds r g b p3.4 cor rgbref frame v ddm oscgnd v ddt v dda v ssd2 sda scl rc a0 saa5290 eeprom pcf8582e a1 a2 v dd v ss v dd v dd v dd 100 nf 47 m f v dd 4.7 k w tv control signals ir receiver v dd v dd 2.2 m f 12 mhz v dd v dd 100 nf 47 m f field flyback line flyback to tv's display circuits v dd 1 k w 10 k w 3.3 k w 100 nf ph2369 1 k w fig.11 typical application diagram.
february 1995 32 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 package outline fig.12 plastic shrink dual in-line package; 52 leads (600 mil) sdip52, sot247-1. dimensions in mm. handbook, full pagewidth 1 27 26 1.3 max 14.1 13.7 47.92 47.02 4.57 max 5.08 max 0.51 min 3.2 2.8 seating plane 0.18 m 0.53 max 1.778 (25x) 1.73 max 15.80 15.24 0.32 max 15.24 17.15 15.90 msa267 52
february 1995 33 philips semiconductors preliminary speci?cation one page economy teletext/tv microcontroller saa5290 soldering plastic dual in-line packages b y dip or wave the maximum permissible temperature of the solder is 260 c; this temperature must not be in contact with the joint for more than 5 s. the total contact time of successive solder waves must not exceed 5 s. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply the soldering iron below the seating plane (or not more than 2 mm above it). if its temperature is below 300 c, it must not be in contact for more than 10 s; if between 300 and 400 c, for not more than 5 s. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.

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